Speed and Area Efficient Reconfigurable Viterbi Decoder using Hybrid Approach |
Author(s): |
| Dinesh Kumar , National Institute of Technical Teacher Training & Research, Chandigarh (UT) |
Keywords: |
| Convolutional Encoder, Viterbi Decoder, Verilog Alpha-Lipoprotein, Viterbi Formula |
Abstract |
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A Viterbi algorithm for decoding of the convolutional code is a powerful method for controlling errors in data transmission over a noisy channel. It is based on maximum likelihood algorithm for decoding the data. However, the hardware implementation of Viterbi algorithm become crucial as it consumes large resources due to its complexity. This paper discussed the implementation of Hybrid Viterbi decoder in VHDL using ModelSim and Xilinx 13.3 ISE tools for simulation and synthesis of modules respectively. |
Other Details |
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Paper ID: IJSRDV5I21492 Published in: Volume : 5, Issue : 2 Publication Date: 01/05/2017 Page(s): 1575-1577 |
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