Design and Analysis of High Performance Multipliers using VHDL

Today every digital circuit has to face the power consumption issues. The design of an efficient integrated circuit in terms of power, area and speed simultaneously, has become a very challenging problem. Power dissipation is recognized as a critical parameter in modern VLSI design field. Multiplication is a binary mathematical operation of scaling one number by another. A fast and energy efficient multiplier is always needed in electronics industry especially DSP, image processing and arithmetic units in microprocessors. In this work high performance multiplier architecture is proposed, by the use of shift-and add and booth multiplier approaches. Low power consumption can be achieved through some modifications in the conventional multiplier architectures. By the use of these multiplier approaches, power consumption can be achieved through the reduction of partial product generation. The proposed multiplier architectures will reduce the number stages in multiplication and also reduces the propagation delay in digital circuits. The system will be designed by using VHDL (Very High speed integrated circuit Hardware Descriptive Language).