High Speed Vedic Multiplier Used Vedic Mathematics |
Author(s): |
| Dravik K. Kahar , Parul University; Harsh Mehta, Parul university |
Keywords: |
| Vedic Mathematics, FPGA, MAC, Multiplier |
Abstract |
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Multiplier is one of the most important part in any processor speed, which improves the speed of the operation like in special application processors like Digital Signal Processor (DSPs). Now I propose a method, which is faster multiplication technique by using Vedic mathematics formula Urdhava Tiryakbhyam method means vertically, and cross wise. Vedic mathematics is mainly based on sixteen Sutras and was rediscovered in early twentieth century. In ancient India, this Sutra was traditionally used for decimal number multiplications within less time. The same basic concept is applied for multiplication of binary numbers to make it useful in the digital hardware. The speed of the computation process is increased and the computing time is reduced due to decrease of path delay compared to the existing multipliers. |
Other Details |
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Paper ID: IJSRDV5I30159 Published in: Volume : 5, Issue : 3 Publication Date: 01/06/2017 Page(s): 60-62 |
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