Study and Analysis of CMOS Inverter and Layout Implementation |
Author(s): |
| Harikesh Chandra Jaiswal , Suyas institute of information and Technology, Gorakhpur-273016, Uttar Pradesh, India; Sangam Kumar, madan mohan malviya university of Technology, Gorakhpur-273010, Uttar Pradesh, India; Anushree Srivastava, Suyas institute of information and Technology, Gorakhpur-273016, Uttar Pradesh, India |
Keywords: |
| Power, CMOS Inverter, Layout Implementations |
Abstract |
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In this paper, Complementary Metal Oxide Semiconductor (CMOS) is analyzed for application to low power, mixed signal environments. A small CMOS cell library is developed and optimized for several different performance requirements. The cells are then applied to the generation of ripple adders and pipelined CORDIC structures and compared with equivalent MCML circuits. CMOS CORDICs are designed which can operate from 130MHz to 330MHz with power consumption varying between 4.5mW and 18.8mW. These power results are up to 1.5 times less than MCML CORDICs, with equivalent propagation delays. Design was done in a 0.25ïm standard MCML process from ST Microelectronics. |
Other Details |
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Paper ID: IJSRDV5I31061 Published in: Volume : 5, Issue : 3 Publication Date: 01/06/2017 Page(s): 1230-1234 |
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