Gate Diffusion Input Full Subtractor Circuit using 130nm Technology |
Author(s): |
| Korade Tushar Tukaram , AMRUTVAHINI COLLEGE OF ENGINEERING,SANGAMNER.DIST-AHAMEDNAGAR,MH; Sandip B. Rahane, AMRUTVAHINI COLLEGE OF ENGINEERING,SANGAMNER.AHAMEDNAGAR,MH |
Keywords: |
| Low Power, Power Delay Product, Semiconductor Device Count, GDI Technique, High Speed |
Abstract |
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A full subtractor circuit based on Gate Diffusion Input (GDI) technique has been presented in this paper. The circuit has been realized with lesser transistor count and achieves low power consumption. The circuit design is performed in 130nm technology and performance is compared with CMOS, transmission gate (TG) and Complementary Pass Transistor Logic (CPL). The proposed circuit achieves a benefit of 72 %, 63 % and 59 % in terms of semiconductor device count respectively for CMOS, TG and CPL. Average power consumed is as low as 589.68µW. The circuit exhibits a delay of 100ns. The proposed GDI subtractor design is simulated in a Mentor Graphics EDA tool environment. |
Other Details |
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Paper ID: IJSRDV5I40819 Published in: Volume : 5, Issue : 4 Publication Date: 01/07/2017 Page(s): 655-658 |
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