Design of 4-bit Reversible Multiplier Circuit Using Conventional Reversible Parallel Adders |
Author(s): |
| Rasamalla Sandeep , Kakatiya Institute of Technology & Sciences; S. Narender, Kakatiya Institute of Technology & Science |
Keywords: |
| Reversible Circuits, Multiplier, Quantum Architectures, Garbage Output, Constant Input |
Abstract |
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In this paper a new reversible device conventional reversible parallel adder is used to design a novel reversible 4-bit binary multiplier circuit. It has been shown that the proposed reversible logic device in designing multiplier circuits can work singly as a reversible full adder. Furthermore the proposed full adder will be of great help in reducing the garbage outputs and constant inputs parameters. The proposed multiplier can be generalized for NxN bit multiplication. Thus, this job will be of significant value as the technologies mature. |
Other Details |
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Paper ID: IJSRDV5I41005 Published in: Volume : 5, Issue : 4 Publication Date: 01/07/2017 Page(s): 981-984 |
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