Energy Efficient Performance Dynamic CMOS XOR/XNOR Gate Design |
Author(s): |
| Aditya Mishra , Vidyapeeth Institute of Science & Technology Bhopal; Deepak Kumar, Vidyapeeth Institute of Science & Technology Bhopal |
Keywords: |
| Energy Efficiency; Hybrid CMOS Logic; Layout Area; Three Input XOR/XNOR |
Abstract |
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This work presents a review on three input XOR/XNOR gate intended for advanced microprocessor inbuilt arithmetic and logic unit (ALU). The objectives are to reduce energy consumption. Traditional dynamic N-Type, dynamic P-Type and new hybrid type systematic cell design methodology (SCDM) is designed and compare with proposed on the basis of following parameter like delay, leakage power, energy consumption, and layout area. Recently published method utilizes the concept of current mirror circuit to improve the performance of dynamic XOR//XNOR. It is observed that the new design has lower energy dissipation and small layout area. In this work, results are simulated at 130nm technology. |
Other Details |
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Paper ID: IJSRDV5I50926 Published in: Volume : 5, Issue : 5 Publication Date: 01/08/2017 Page(s): 981-983 |
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