Implementation of Direct Digital Synthesizer using Cordic Processor

This paper presents the Design and Implementation of Direct Digital Synthesizer using Rotation mode Pipelined CORDIC (CO-ordinate Rotation Digital Computer) algorithm. Direct Digital Synthesizer (DDS) is heart of many Digital Communication Systems such as Digital Radio and Modems, modulators, mixers, sound synthesizers, Digital Down/Up converters etc. The algorithm used in this paper uses dynamic transformation instead of ROM static addressing which reduces area requirement and improves the performance. The pipelined architecture enables us to calculate continuous input with high throughput. In this paper, DDS design is designed using verified Verilog HDL and then stimulated and optimized using Questasim 10.1. The Verilog code is then synthesized using Xilinx 12.1 for hardware realization. The power report for the design is generated using Cadence tool The Designs are verified on Xilinx Spartan6 FPGA Development Platform.