Design & Performance Analysis of Low Power Parity Preserving Carry-Look Ahead Adder

In this technological world, development in the field of nano-technology leads to minimize the power consumption of logic circuits. Reversible logic design is one of the promising technologies gaining greater interest due to less dissipation of heat and low power consumption. In this paper, an optimized design of reversible 2-bit and 4-bit parity preserving carry look ahead adder is proposed that uses only two reversible gates i.e. F2G and MFRG gates and consumes low power. Systems where low power consumption is required, reversible logic gates will be used in place of classical logical gates like AND, OR, NAND, NOR. The proposed design offers an improvement of 15.67% and 50% over the existing design in terms of its Quantum cost & Power consumption respectively. Reversible or information-lossless circuits have applications in digital signal processing, communication, computer graphics and cryptography.