Improve Performance Static Random Access Memory Based on Design PLPSRAM

In this field research paper explores the design and analysis of Static Random Access memories (SRAM) that focuses on optimizing delay and power. CMOS SRAM cell consumes very less power and have less read and write time. Higher cell ratios will decrease the read and write time and improve stability. PMOS semiconductor unit with less dimension reduces the ability consumption. Our propose design propose low power static access memory (PLPSRAM) cell is implemented with reduced power and performance is good according read and write time, delay and power consumption. It’s been noticed typically that increased memory capability will increase the bit-line parasitic capacitance that successively slows down voltage sensing, to avoid this drawback use optimized scaling techniques and more, get improve performance of the design. Memories are a core a part of most of the electronic systems. Performance in terms of speed and power dissipation is that the major areas of concern in today’s memory technology. PLPSRAM cells supported 6T, 10T configurations are compared on the basis of performance for read and write operations. during this paper completely different static random access memory are designed so as to satisfy low power, high performance circuit of our propose design circuit PLPSRAM.