Design and Implementation of High Speed Carry Select Adder using GDI Technique for Low Power Applications

Addition is a fundamental arithmetic operation usually worn in VLSI systems. The increasing demands for high speed and high resolution mixed signal integrated circuits dictate the use of Gate Diffusion Input (GDI) technique in contrast to traditional CMOS logic style. Simultaneous fulfillment of demands causes the need for the adders that has high speed and low power consumption. Solution comes to an end by the design of GDI adders. GDI is a logic style that appears to be promising in reducing power consumption, increasing speed and providing an analog and digital friendly environment. GDI technique is a novel technique which is extension of GDI (gate diffusion input) technique for low power digital circuits design further to reduce the swing degradation problem. This paper presents logic style comparisons based on different logic functions and claimed Gate Diffusion Input logic (GDI) to be much more power-efficient than complementary CMOS logic design. This technique can be used to reduce the power consumption compared to existing SQRT BK CSA using BEC, This techniques allows reduction in power consumption, carry propagation delay and transistor count of the carry select adder. Thus, the implementations of different GDI adders have been suggested in this thesis. The work shows that proposed Carry Select Adder using GDI technique has less area and consumes less power. Also it provides reduced delay comparatively and therefore can be used in various processors in order to perform fast arithmetic operations.