Performance of 6T FinFET SRAM and 6T CMOS SRAM Cell |
Author(s): |
| Sundeep Kaur , Punjabi University Patiala; Mandeep Kaur, Punjabi University Patiala |
Keywords: |
| PDP, SNM, SOI, Access Time and HSPICE |
Abstract |
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As innovation is scaling down and superior device requirements is extending including low power utilization, high versatility, high speed, low leakage currents, high dependability and small region so that Moore’s Law will be followed in the up and coming years too. In this paper conventional 6T and 9T SRAM cell is designed utilizing MOSFET, FinFET at 16nm and 45nm technology node and its performance parameters, for example, power, delay, Power Delay Product (PDP). The simulation has been finished with HSPICE tool for transient and dc analysis. |
Other Details |
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Paper ID: IJSRDV5I60632 Published in: Volume : 5, Issue : 6 Publication Date: 01/09/2017 Page(s): 2131-2135 |
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