Performance Analysis of 8 Transistor One-Bit Full Adder in 130nm CMOS Technology |
Author(s): |
| Ritu Adhikari , B.T.K.I.T Dwarahat,Almora; Rachna Arya, B.T.K.I.T Dwarahat,Almora |
Keywords: |
| CMOS, Delay, Full Adder, PDP, XOR-XNOR Gates |
Abstract |
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This paper discusses the evolution of full adder circuit in terms of lesser power consumption. A High performance Low-power design is the demand of today's world. A Full adder is a basic and most important digital component. Adders are commonly used in microprocessor and digital signal processing chips. Proposed full adder cell implemented using XNOR-XOR (2T) design style. Pass transistor logic has been used to implement the XNOR gate and an inverter is used for implementation of XOR gate. Here the proposed full adder design compared with conventional full adder. The comparison is made on the basis of power dissipation, delay, and PDP. All the simulation work had been done on 130nm CMOS technology. The schematic of circuit and simulation is done using Pyxis Mentor Graphics software. |
Other Details |
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Paper ID: IJSRDV5I70407 Published in: Volume : 5, Issue : 7 Publication Date: 01/10/2017 Page(s): 808-812 |
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