Designing of a CMOS NAND Gate Using INDEP With Bi-Triggering (Trig01) Method |
Author(s): |
| Aloka Tamta , B.T.K.I.T Dwarahat, Almora; Rachna Arya, B.T.K.I.T Dwarahat, Almora |
Keywords: |
| EH-WSN, MS, ECR, ERR, ICGS, ICA, GS |
Abstract |
|
In deep submicron process power consumption is one of the major concerns in CMOS circuits. Moving to finer technologies for high transistor density and smaller equipment size as per the market demand, leakage power is increasing rapidly, due to reduced voltage and oxide thickness. In this paper a new leakage power reduction technique is proposed which is a combination of two approaches namely INDEP Approach and Trig01 (Bi-Triggering) Approach. The simulation is done at 130nm process technology using Mentor Graphics Back End Tool with Pyxis Schematic 10.5 version on Linux Operating System. Significant power reduction is achieved with reduction in propagation delay and power delay product. |
Other Details |
|
Paper ID: IJSRDV5I70478 Published in: Volume : 5, Issue : 7 Publication Date: 01/10/2017 Page(s): 935-938 |
Article Preview |
|
|
|
|
