Design and Implementation of Low Delay Look Ahead Adder and Ripple Adder |
Author(s): |
| Samrat Kumar Singh , VIST,Bhopal; Deepak Kumar, VIST,Bhopal |
Keywords: |
| Adder, Ripple Carry Adder, Carry Look-Ahead Adder, Carry Select Adder VHDL Code |
Abstract |
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In recent years, a lot of attentions have been attracted by the reversible logic due to the characteristic of zero energy dissipation. In this paper, the author proposed a 16 bit carry look-ahead adder is constructed by four 4 digits groups based on the theory of reversible logic, which has the advantages of theoretical zero power dissipation and high efficiency. This paper focuses on the implementation 16 and bits of highly optimized area efficient Ripple carry adder (RCA) and Carry look ahead (CLA) adders. Ultimately, we can establish that the Carry look ahead adders are so greatest among all the formerly active designs. All these processes will be Simulated & Synthesized on the ISE Xilinx 14.7 software. |
Other Details |
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Paper ID: IJSRDV5I80160 Published in: Volume : 5, Issue : 8 Publication Date: 01/11/2017 Page(s): 75-78 |
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