FPGA Implementation of 16*16 Vedic Multiplier in VHDL Environment |
Author(s): |
| Smruti Ranjan Nayak , CENTURION UNIVERSITY OF TECHNOLOGY & MANAGEMENT; Ritisnigdha Das, CENTURION UNIVERSITY OF TECHNOLOGY & MANAGEMENT; S. K Saifur Raheman, CENTURION UNIVERSITY OF TECHNOLOGY & MANAGEMENT |
Keywords: |
| FPGA, FFT, DSP, RTL, EDA |
Abstract |
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A high speed processor depends greatly on the multiplier in most digital signal processing system as well as in general processor. Currently the speed of the multipliers is limited by the speed of the adders used for partial product addition. It is an ancient methodology of Indian mathematics as it contains 16 SUTRAS (formulae). A high speed complex 16 *16 multiplier design by using urdhvatiryakbhyam sutra is presented in this paper. By using this sutra the partial products and sums are generated in one step which reduces the design of architecture in processors. It can be implemented in many Digital Signal Processing (DSP) applications such as convolution, Fast Fourier Transform (FFT) filtering and in microprocessors. By using this method we reduce the propagation delay in comparison with array based architecture and parallel adder based implementation which is most commonly used architecture. |
Other Details |
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Paper ID: IJSRDV5I80371 Published in: Volume : 5, Issue : 8 Publication Date: 01/11/2017 Page(s): 381-383 |
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