Review Work on Differential Read and Write based SRAM Cell |
Author(s): |
| Ms. Jaya Sahu , IES College of Technology, Bhopal; Mr. Ashish Raghuwanshi, IES College of Technology, Bhopal |
Keywords: |
| Cache Memory, Hold Power, Read/Write Access Time and Noise Margin |
Abstract |
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Scaling in Silicon technology, usage of SRAM Cells has been increased to large extent while designing the embedded Cache and system on-chips in CMOS technology. Power consumption, packing density and the speed are the major factors of concern for designing a chip. This review focuses on the design of a novel low power twelve transistor static random access memory cell. SRAM can be categorised on the basis of no. of terminal used for read/write, region of operation(subthreshold), multi-threshold MOSFET based, power consumption, noise margin, read/write delay time and transistor count. |
Other Details |
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Paper ID: IJSRDV5I80426 Published in: Volume : 5, Issue : 8 Publication Date: 01/11/2017 Page(s): 629-632 |
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