Review Work on XOR Logic Gate Design using MOSFET |
Author(s): |
| Ms. Poojashree Sahu , IES College of Technology, Bhopal; Mr. Ashish Raghuwanshi, IES College of Technology, Bhopal |
Keywords: |
| Power-Delay-Product; Hybrid CMOS Logic; Transmission Gate; Layout Area; XOR/XNOR Gate |
Abstract |
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Full Adder is one of the smallest unit used in the complex data processing to perform fast arithmetic operations. The main aim of this paper is a design of systematic cell design methodology (SCDM) based XOR gate with three input. The XOR gate is an absolutely necessary primitive in the design of full adder cell for sum generation. Intension behind a novel SCDM based design is to improve speed and reduce power dissipation. Traditional dynamic N-channel FET, dynamic P-channel FET and new hybrid type systematic cell design methodology (SCDM) is designed and compare with proposed on the basis of following parameter like propagation delay, average power consumption, energy consumption, and layout area. It is observed that the new design has lower power dissipation, lower energy consumption, less delay and small layout area. |
Other Details |
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Paper ID: IJSRDV5I80427 Published in: Volume : 5, Issue : 8 Publication Date: 01/11/2017 Page(s): 639-641 |
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