Overall Performance Assessment of Skip Transistor and CMOS Logic Configuration Primarily Based De-Multiplexers

Speed and the overall performance of any digital signal processor are largely determined by the efficiency of the de-multiplexer units present within. The use of pass transistor logic has resulted in significant improvement in the performance of de-multiplexer architectures used for high speed computing. This paper proposes 1 to 2, 1 to 4 and 1 to 8 de-multiplexer architectures based on pass transistor logic. These low power designs are realized in 65 nm CMOS Process technology using Microwind and DSCH 3.5 tool. This research paper analyses the performance of De-Multiplexer (De-Mux) using Pass Transistor Logic Configuration (PTLC) and CMOS Logic Configuration (CLC). Furthermore, a comparison between the performances of both the configurations in terms of power and area. Besides this, paper also signifies more than 50% decrement in area and number of transistors count while using pass transistor logic configuration in comparison to de-multiplexer implemented with CMOS logic configuration. Moreover, reduction in power dissipation up to 70% is observed in pass transistor logic comparing to CMOS logic.