Implementation of Minimum Delay and Low Power 32 Bit Arithmetic Logic Unit |
Author(s): |
| Aditi Shrivastava , VNS group of institution Bhopal; Anil Khandelwal, VVNS group of institution Bhopal |
Keywords: |
| Arithmetic Logic Unit, VHDL |
Abstract |
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In this paper VHDL implementation of 64-bit arithmetic logic unit is presented. The design was implemented using VHDL Xilinx Synthesis tool ISE 14.7 and targeted for virtex4 device. ALU was designed to perform arithmetic operation and logical operations such as addition, subtraction using 64-bit fast adder, logical operations such as AND, OR, XOR and NOT, NOR, NAND operations. ALU consist of two input registers to hold the data during operation, one output register to hold the result of operation. The maximum propagation delay is 33.468nsand power dissipation is 0.166nW. |
Other Details |
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Paper ID: IJSRDV5I90326 Published in: Volume : 5, Issue : 9 Publication Date: 01/12/2017 Page(s): 1087-1089 |
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