Pipeline Concept for Implementing High Speed and Low Area Digital Radix-2 CSD Multipliers

There are many types of algorithms or multipliers available in literature, Such as Modified Booth multiplier, Wallace tree multiplier, Radix-2 CSD multiplier and so on. Especially, there have been extensive researches about Radix-2 CSD multipliers as CSD numbers represented with lesser number of non-zero digits. In this paper, a study on various techniques of CSD conversions and best of these conversions is applied to different CSD multipliers. Horner method based multiplication is taken as reference in this paper. It reduces complexity. But, it faces the problem of high power consumption along with low speed. In this paper, Pipeline based multiplication is proposed which eliminates above said problems. This method saves execution time by 87.96% time and reduces number of slice LUTs by 92.86% in comparison with the earlier method (Horner based) while designing them in Verilog HDL and targeted on Xilinx Vertex-7 device.