Implementation of Multipliers using Symmetric Stacking Method |
Author(s): |
| Mr. E. Aravindhan , Mepco Schlenk Engineering College,Sivakasi; Ms. S. Dhivya, Mepco Schlenk Engineering College,Sivakasi; Ms. J. Angel Anu Princy, Mepco Schlenk Engineering College,Sivakasi |
Keywords: |
| Symmetric Stacking Method |
Abstract |
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In this brief, a Counter based multiplier using Symmetric Stacking method is proposed. In this method, a 3-bit Stacking circuit is used which groups 1’s followed by 0’s and then the 3-bit Stack is combined to form a 6-bit Stack by a novel Symmetric method. The Output of this circuit is converted into binary count producing a 6:3 Counter circuit with no XOR gates on its critical path. The proposed Counter is efficient when compared to existing parallel counters in terms of latency. Additionally, implementation of proposed counter in Wallace and Dadda multipliers reduces the latency compared to the conventional method. |
Other Details |
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Paper ID: IJSRDV6I11168 Published in: Volume : 6, Issue : 1 Publication Date: 01/04/2018 Page(s): 1918-1921 |
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