Low Power High Speed Estimated Reconfigurable Multiplier for Multimedia Signal Processing

Rapid development of VLSI design, the logic gates and arithmetic circuits plays important role in signal, image, video and microprocessor applications. A challenging problem in hardware design is to develop hardware efficient, high speed and low power design. Multiplication is one of the arithmetic operations for such applications. Most of the existing multipliers satisfy single requirement, but the time delay and power consumption are very essential requirements for such applications. In this paper, we propose an approximate reconfigurable (AR) multiplier obtained by scaling the input operands. The objective of proposed AR multiplier is to enhance the speed and power consumption at the price of low hardware cost. The scaling logic is used to compute the least significant part of the result is kept in a steady state, as the adders input do not change; the switching activity of this logic is 0, while the unfrozen part of the adder still has a switching activity. Moreover, AR multiplier with the n-bit operation is designed by the canonical signed-digit (CSD) technique for reducing number of adders/shifters in the design. The implementation of the proposed AR multiplier is evaluated by comparing it is performance with state-of-art multipliers in terms of hardware utilization, maximum clock frequency and power consumption.