Design and Analysis of First in First out using Different Read and Write Logics in Verilog |
Author(s): |
| Kalaiselvi P , Mahendra Engineering College; Ravikumar M, Mahendra Engineering College |
Keywords: |
| CPLD; FIFO; FTU; Data Cache; Real-Time Monitoring |
Abstract |
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FIFO is an approach for handling program work requests from queues or stacks so that the oldest request is handled first. In hardware, it is either an array of flops or read/write memory that stores data from one clock domain and on request supplies the same data to other clock domains following FIFO logic. Through analyzing on the FIFO module characteristics, we design and analyses FIFO using different read and write logics. We have considered 64 inputs, each having 32-bit data, and all of its feature implementations are described using Verilog HDL. At present, the scheme has been applied in the systems of distribution feeder automation, through detecting, which meets the system performance demands. |
Other Details |
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Paper ID: IJSRDV6I120389 Published in: Volume : 6, Issue : 12 Publication Date: 01/03/2019 Page(s): 542-544 |
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