Interfacing of I2C Master Bus Controller on FPGA for Single Chip Serial Communication |
Author(s): |
| M. Mohan Kumar , SRI ESHWAR COLLEGE OF ENGINEERING; R. Anantha Lakshmi, SRI ESHWAR COLLEGE OF ENGINEERING; E. Bhuvaneshwari, SRI ESHWAR COLLEGE OF ENGINEERING; S. Bhuvaneshwari, SRI ESHWAR COLLEGE OF ENGINEERING |
Keywords: |
| I2C, MAXIM DS1307, FPGA, VHDL, On-Chip, Low-Speed Peripherals, Xilinx |
Abstract |
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This paper is on I2C protocol following master controller. All I2C bus are compatible devices incorporate an on-chip interface which allows them to communicate directly with each other via an I2C bus. I2C Master bus design concept solves many interfacing problems encountered when designing digital circuits. This paper implements I2C (Inter-Integrated Circuit) master bus controller for interfacing low-speed peripheral devices using field programmable gate array (FPGA). The I2C master bus controller interfaced with slave device Real Time Clock (MAXIM DS 1307). The interface module was designed using VHDL. The design was synthesized using Xilinx ISE and implemented on FPGA. |
Other Details |
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Paper ID: IJSRDV6I20077 Published in: Volume : 6, Issue : 2 Publication Date: 01/05/2018 Page(s): 196-199 |
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