Design and Implementation of Binary Adder using FPGA |
Author(s): |
| Shwetal Wankhede , MIET SHAHAPUR, BHANDARA, RTM NAGPUR UNIVERSITY; Sayli Kale, MIET SHAHAPUR, BHANDARA, RTM NAGPUR UNIVERSITY; Rupali Bawankule, MIET SHAHAPUR, BHANDARA, RTM NAGPUR UNIVERSITY; Vinod Buddhe, ASSITANT PROFESSOR IN MIET SHAHAPUR, BHANDARA, RTM NAGPUR UNIVERSITY |
Keywords: |
| Adder, Ripple Carry Adder, Carry Look Ahead Adder, Carry Select Adder, FPGA |
Abstract |
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This paper present the design method and simulation statergy of 32-bit ripple carry adder using Verilog HDL on xillinx. To implement this large adder, simple gates, 4-bit adder and 16-bit adder blocks are used separately. Adder is very basic unit in most of the digital processing unit the speed of computer becomes the most important condition for designer. We have taken different analysis on the basis of parameter like area (Form factor) and speed of different adders like ripple carry adder, carry select adder and carry look ahead adder. We found that ripple carry adder is faster than other adders. We have successfully designed 32-bit ripple carry adder in Spartan 3 series FPGA. We present synthesis and simulation results verified using Xilinx. Our results are comparing with previously designed adder and found that our design unit is efficient as compare to others. |
Other Details |
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Paper ID: IJSRDV6I20367 Published in: Volume : 6, Issue : 2 Publication Date: 01/05/2018 Page(s): 466-467 |
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