Implementation and Performance Analysis of Divide-by-4/5 Dual Modulus Prescaler |
Author(s): |
| Reena Sisodiya , L. D. College of Engineering; Chirag M. Senjaliya, L. D. College of Engineering; Dr. Mihir V. Shah, L. D. College of Engineering |
Keywords: |
| Phase Locked Loop (PLL), True Single-Phase Clocking (TSPC), Dual Modulus Prescaler (DMP), Flip Flop (FF), PVT (Process-Voltage-Temperature) |
Abstract |
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The prascaler is a significant unit in phase locked loop (PLL) which is extensively used in RF frequency synthesizer. The implementation technology is 45 nm bulk CMOS technology. This paper presents divide-by-4/5 dual modulus prescalers based on True Single Phase Clocked (TSPC) logic which can be used to design multi-modulus or programmable prescaler. This design consumes the 0.93mW and 1.11mW power for divide-by-4 and divide-by-5 operation respectively. The simulation was performed at 4 GHz frequency with supply voltage 1V. The summary of performance parameters of the proposed prescaler with previously reported work is given in terms of operating frequency, supply voltage, power dissipation and propagation delay. |
Other Details |
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Paper ID: IJSRDV6I21313 Published in: Volume : 6, Issue : 2 Publication Date: 01/05/2018 Page(s): 2082-2085 |
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