Design of Systolic Array Architecture for Matrix Multiplication Inference on FPGA

For data transmission, an ideal communication relies on Low Power Design. Systolic array multiplier with logic is widely known among those techniques for synchronizing signals in DSP processor applications. Low power circuit design yields many favorable conditions like increased performance, system capacity, minimized cost etc. Among basic arithmetic operations, Multiplication demands more processing time and seek complex hardware. As Conventional Systolic Array Multiplier is designed using logic gates, there is undesired power dissipation. . FPGA is used to obtain simulation results. Power for the proposed design when the power of individual components. In recent years, the FPGA implementation has attracted much attention because of its high performance and energy efficiency. However, existing implementations have difficulty to fully leverage the computation power of the latest FPGAs So, to improvise this downside, this paper illuminates the design of low power Systolic Array Multiplier using logic gates which performs data processing in concurrent manner. Power dissipation, time delay, outputs and cost is calculated mathematically. In this paper we implement on an FPGA using a systolic array architecture, which can achieve high clock frequency under high resource utilization. We provide an analytical model for performance and resource utilization and develop an automatic design space exploration.