Hardwired BIST Architecture of SRAM |
Author(s): |
| Sonam Rawat , P.K.University, Thanra, Shivpuri, MP; Vikas Gupta, P.K.University, Thanra, Shivpuri, MP |
Keywords: |
| Built in Self-Test Circuit under Test, Device under Test, IC, SOC, Register Faults, CRC |
Abstract |
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As the compactness of system on chip (SoC) increase, it becomes striking to integrated test logic on a chip. Starting with a broad idea of test problems, this survey paper on focus on "Chip" Built in Self-Test (BIST) study and its promotion for board and system level application. It became highly important to test various kinds of defects rapidly and precisely to reduce the testing cost and to improve the memory quality especially in a SoC (System on a Chip)design environment .memory defects can be moduled as struck-at, coupling, transition address decoder, and pattern sensitive feels. Recently BIST research is being highly used in VLSI and SoC testing for the detection fault coverage. |
Other Details |
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Paper ID: IJSRDV6I30574 Published in: Volume : 6, Issue : 3 Publication Date: 01/06/2018 Page(s): 940-943 |
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