Design Of 5T S-Ram Cell with Low Leakage Current using VLSI Technology |
Author(s): |
| Aditya Shamgule , HVPM'S COLLEGE OF ENGINEERING AND TECHNOLOGY AMRAVATI,INDIA; Karuna Shendre, HVPM'S COLLEGE OF ENGINEERING AND TECHNOLOGY AMRAVATI,INDIA; Swapnil Nimkar, HVPM'S COLLEGE OF ENGINEERING AND TECHNOLOGY AMRAVATI,INDIA; Kirtimala Kumeriya, HVPM'S COLLEGE OF ENGINEERING AND TECHNOLOGY AMRAVATI,INDIA; Dr. U. A. Kshirsagar, HVPM'S COLLEGE OF ENGINEERING AND TECHNOLOGY AMRAVATI,INDIA |
Keywords: |
| SRAM, VLSI Technology, CMOS Technology |
Abstract |
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A new single-port five-transistor (5T) Static Random Access Memory (SRAM) cell with integrated read/write assist is proposed. Amongst the assist circuitry, a voltage control circuit is coupled to the sources corresponding to driver transistors of each row memory cells. This configuration is aimed to control the source voltages of driver transistors under different operating modes. Specifically, during a write operation, by means of sizing the driver transistor close to bit line to resolve the write '1' issue. In addition, associated with a two-stage reading mechanism to increase the reading speed and to avoid unnecessary power consumption. Finally, with the standby start-up circuit design, the cell can switch to the standby mode quickly, thereby reduce leakage current in standby. |
Other Details |
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Paper ID: IJSRDV6I30952 Published in: Volume : 6, Issue : 3 Publication Date: 01/06/2018 Page(s): 1918-1920 |
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