A Clocked High Speed Comparator Design on Cadence Virtuoso 90nm CMOS Technology

The proposed work envisages increasing the sampling frequency of Analog to Digital converts which directly affects their speed while simultaneously decreasing the power consumption which increases the practical applicability of the circuits and renders thermal stability. The low power, high speed and area efficient Analog to Digital Converters (ADCs) use widely dynamic regenerative comparators to maximize their power efficiency, operation speed and area. In this work, a new high clock (sampling frequency ) dynamic comparator is proposed based on double tail architecture, where the circuit of a conventional double tail comparator is modified to operate at higher frequencies with reduced energy per conversion (energy required to convert a signal into samples) at low supply voltage. In the proposed comparator, a modification in the form of an extra transistor (control transistor) has been added to the previous circuit along with a reduction in the length of the MOSFET transistor from 180nm to 90nm. This comparator circuit is designed and simulated on the tanner EDA tool. The proposed double tail comparator achieves a maximum clock frequency up to 3 GHz at a supply voltage of 1.2V.