Development of Ultra Low Power VLSI Design using various Low Power Design Techniques |
Author(s): |
| K Shirisha , auroras technological and research institute; T Siva Prasad, AAR mahaveer engineering college |
Keywords: |
| Leakage Power, Power Dissipation, Low Power, CMOS Technologies |
Abstract |
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Leakage power plays a vital role in current CMOS technologies. As feature size shrinks leakage power also increasing. Power dissipation becomes as important consideration as performance and area for chip design in present days VLSI industry. International Technology Roadmap for Semiconductors (ITRS) forecasts that sub threshold leakage power dissipation may dominate the dynamic power dissipation. There are two types of power dissipations in CMOS technologies those are static power dissipation and Dynamic power Dissipation. This paper mainly concentrates on static power dissipation, in that mainly on leakage power. This paper reviews various low leakage power design techniques to achieve low power dissipation. |
Other Details |
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Paper ID: IJSRDV6I40607 Published in: Volume : 6, Issue : 4 Publication Date: 01/07/2018 Page(s): 736-739 |
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