Dead Time Controlled Gate Driver using FET Integrated in Sic MOSFET

Power gating is the most effective method to reduce the standby leakage power by adding header/footer high-VTH sleep transistors between actual and virtual power/ ground rails. When a power gating circuit transitions from sleep mode to active mode, a large instantaneous charge current flows through the sleep transistors. Ground bounce noise (GBN) is the high voltage fluctuation on real ground rail during sleep mode to active mode transitions of power gating circuits. GBN disturbs the logic states of internal nodes of circuits. A novel and reliable power gating structure is proposed in this article to reduce the problem of GBN. There are also many problems like ultra-low voltage regimes suffer the signal strength problem. The Gate Diffusion Input requires twin well CMOS or silicon on insulator (SOI) process for fabrication. All these problems are resolved with the help of inverter circuit to remove the GBN noise with SIMULINK and Monte Carlo model. The MOSFET is applied to improve the thresholding and voltage loss in circuit.