Low Power Dynamic Comparator Design using 0.18 Micrometer CMOS Technology at 1v Power Supply

A comparator is very integral and important block in analog to digital converter circuits. Its performance affects the performance of ADC. Speed, low offset voltage and low power consumption are the key parameter in designing the comparator. Over the year’s low power and low voltage comparator design has become very critical. As the power supply decreases the offset voltage increases but to reduce the power consumption it is essential to reduce the supply voltage. Dynamic comparators can do the needful that can reduce the offset voltage by reducing the mismatch between the transistors. A dynamic comparator is been shown in this paper that has less number of transistors. Cross coupled CMOS inverters are used at the decision section to provide the positive feedback. Two clock phases are used to operate amplifier and decision section. By doing so the offset voltage can be minimized. The design is simulated at 0.18 µm CMOS technology at 1 V supply voltage. 100 MHz clock is used to generate two clock phase, it consumes 162.6 µW power at 1 V supply voltage and 1.13 ns delay.