Review of Fault-Tolerant Routing Algorithms for Network-on-Chip System

Network-on-Chip (NoC) has become one of the regular options in scaling chip multiprocessor (CMP) systems. While scaling networks in deep submicron (DSM) technology and with multiple cores, the NoC systems are subjected to manufacturing defects which results in low productivity, one such defects being the fault issues which reduce the number of available routing paths for packet delivery that will lead to severe traffic congestion finally resulting in a system crash. Therefore this gives rise to the necessity for the fault-tolerant routing algorithm which ensures the correct functioning of system. In order to overcome fault problems, we can employ fault-tolerant routing algorithm, many fault-tolerant routing algorithms such as Modified X-First, Gradient, Minimal and defect-resilient (MD) and PDA-FTR are available which considers path diversity information and buffer information. In this work we are going to make performance analysis of all this algorithms with respect to parameters such as saturation throughput, area and power efficiency for single and multiple faulty routers NoC systems under different traffic scenarios including both synthetic and real traffics. When we compare performance results of these fault-tolerant routing algorithms, it is found that PDA-FTR has improved average saturation throughput with only 8.9 % average area overhead and 7.1 % average power overhead.