Sub 1v Low Dropout Regulator with Low Settling Time |
Author(s): |
| Shriniwas Sudhir Sutar , sinhgad college of engineering; Dr. M. B. Mali, Sinhgad college of Engineering |
Keywords: |
| Capacitor Less Sub 1V LDO; Segmentation Technique; Low Settling Time; Enhanced Stability |
Abstract |
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Owing to the scaled down technology, it becomes obvious to have power management circuitry operating well below 1V and the paper presents design of CMOS Low Dropout Regulator (LDO) serving the purpose. The design is capacitor less approach using Cascode amplifier and two pass devices in parallel so as to enhance the stability & improve the transient response. The circuit works well for supply voltage from 0.9-1.1V & provides 0.8V fixed output. Line & load regulations are 26.22 mV/V & 0.0253 mV/mA. Settling time are 0.97us and 1.32us respective for low to high and high to low transitions. The Quiescent current (IQ) comes out to be 51Õ½A while DC current (IDC) is 65Õ½A. Loop GBW is roughly 2.65MHz with phase margin of well over 100 degrees. The transient response and stability response shows elevated performance compared to the single pass device. |
Other Details |
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Paper ID: IJSRDV6I50448 Published in: Volume : 6, Issue : 5 Publication Date: 01/08/2018 Page(s): 910-912 |
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