Analysis of Double Tail Comparator with Low Power & High Speed Design

Comparators are recognized as 1-bit analog-to digital converter and for that reason they are mostly used in huge abundance in A/D converter. In the analog-to-digital conversion process, it is essential to first sample the input. This sampled signal is then apply to a grouping of comparators to decide the digital equivalent of the analog signal. The conversion speed of comparator is restricted by the decision making response time of the comparator. Besides, comparators are too be found in lots of other applications like zero-crossing detectors, peak detectors, switching power regulators, BLDC operating motors, data transmission, and others. The basic functionality of a CMOS comparator is used to find out whether a signal is greater or smaller than zero or to compare an input signal with a reference signal and outputs a binary signal based on comparison. Comparator is a circuit used to detect whether a signal is greater or smaller than zero, or to compare the size of one signal with another. Designing high-speed comparators is more challenging when the supply voltage is smaller. High-speed comparators in ultra-deep sub-micrometre (UDSM).CMOS technologies suffer from low supply voltages. In this paper we are going to study and analyse the dynamic double tail comparator and implement the same for high speed analysis and will observe the power consumption.