Area Optimized Squaring Method Design using Yavadunam Vedic Math and Tree Adder

Now days we are living in digital world, where all the operations get performed more reliably and with highest accuracy by digital signal processor. There are so many squaring techniques exist now a days at algorithmic and structural level. It is been proved that vedic squaring [1] is the fastest squaring approach but there are some other squaring techniques [1] which are batter then vedic squaring in terms of chip area. We have come up with the idea to merge two different squaring techniques vedic and Wallace and these gives us a fast and area efficient squaring approach. Our proposed ALU algorithm is already efficient in respect of area and speed, all we need to optimize it further to have it we have plan to use our proposed vedic cum Wallace squaring technique on proposed ALU module. We have plan to designing the proposed vedic squaring, then it will be integrated into an 8 bit module of arithmetic logic unit along with the conventional adder, subtractor and basic logic gates. The proposed ALU will able to perform three different arithmetic and eight different logical operations at very high speed. All these operational modules (adder, subtractor, squaring and logic gates) will be designed as the combinational circuit and for synchronization of these operational sub-modules, the multiplexers will be used to integrate these modules in a single unit and triggered by positive edge clock.