1-Bit Full Adder based on Novel Self-controllable Voltage Level Technique for Low Leakage Current

In this work many discharge reduction techniques is studied and analyzed, once that a specific discharge reduction technique is chosen. Hand-picked technique is Self-controllable Voltage Level (SVL) technique. This method is any improved to boost the system of CMOS VLSI circuit. A full adder is that the needed CMOS circuit whose discharge current reduction is decided with the assistance of self manageable voltage level technique. Any we are going to carry our project to cut back discharge current of 4-bit adder. We are going to use Microwind 3.1 and DSCH2 package to style the circuit for coming up with the layout of one-bit adder and 4-bit adder with self manageable voltage level technique. DSCH2 is employed for coming up with the circuit with AND, OR, NOR gates and additionally with transistors. Simulation results of 1-bit adder with improved self manageable voltage level technique are much better than the previous self manageable voltage level technique.