FPGA Implementation of Carry Select Adder using Verilog

A Conventional Carry Select Adder (CSLA) is still power consuming due to the dual Ripple Carry Adder (RCA) structures having Cin as 0 and 1. Hence modifications are done at gate level to reduce power. Modification of CSLA is designed by using Binary to Excess-1 Converter instead of RCA with Cin=1 in the conventional CSLA .This paper proposes an efficient method which replaces the ZCLA instead of RCA with Cin=0 in conventional CSLA and modified CSLA. Thus, the efficient gate level modification helps to reduce the power of CSLA. In this paper the proposed design of 16-bit conventional CSLA using ZCLA is compared with the general modified and conventional versions of CSLA. Carry Select Adder is generally divided into Linear and SQRT CSLA (Non-Linear). In this paper, both CSLA can be implemented in 16 bit conventional, modified and proposed CSLA and the results prove that the SQRT CSLA is better than the Linear CSLA.