32-Bit Full Adder based on Novel Self-controllable Voltage Level Technique for Low Leakage Current |
Author(s): |
| Arman , Sagar Institute of Research & Technology, Bhopal MP, India; Paras Gupta, Sagar Institute of Research & Technology, Bhopal MP, India |
Keywords: |
| Low Leakage Current, Self-Controllable Voltage Level (SVL), VLSI, SoC, CMOS |
Abstract |
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The SVL technique is an improved to boost the system of CMOS VLSI circuit. We are going to use Microwind 3.1 to design the circuit for coming up with the layout of 32-bit adder with self -controllable voltage level technique is a unit many sources for the discharge current, i.e. low threshold voltage. It's appeared that we've to focus to attenuate the discharge current within the range of transistors and also the massive memory substance of future SoC (System on Chip) devices [3]. The main goals of VLSI Designer area unit to cut back the world, improve performance and decreasing the price. Up to 1/2 the overall power consumption is created by leakage power in high performance microprocessors. Leakage current reduction has become a robust tool to a coffee power design. It's turning into a prime priority topic in VLSI circuit design. |
Other Details |
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Paper ID: IJSRDV6I80128 Published in: Volume : 6, Issue : 8 Publication Date: 01/11/2018 Page(s): 262-265 |
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