Advanced Design for DPA Resistant Circuit by using Optimizing Differential Logic Gates |
Author(s): |
| I Kiran Kumar , Baba Institute of Technology and Sciences,Visakhapatnam; K Rajasekhar, Baba Institute of Technology and Sciences,Visakhapatnam |
Keywords: |
| DPA (Differential Power Analysis), Side Channel Attack, Sense Amplifier Based Logic (SABL), Differential Pull Down Network (DPDN), Dynamic and Dual-Rail Gate Logic Style, VLSI 90nm Technology, Single Switch Solution, Differential Logic Gates (AND/NAND, XOR/XNOR, OR/NOR) |
Abstract |
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Differential Power Analysis used in the crypto circuits may be attacked by an another/separate party, using power consumption dependence on secret message/information for hiding critical data (information).To avoid DPA and security basis differential logic styles are basically used, because of constant power dissipation. This paper is also proposed a new design methodology to improvement of pull-down logic configuration for most differential gates are secured. Previously the AND/NAND and XOR/X NOR gates in 90nm VLSI technology, using by SABL (Sense Amplifier Based Logic) for DPDN (Differential Pull down Logic). A new Proposals OR/NOR gates are used to secure/protect Differential logic gates at 90nm technology at 27oC temperature with simulate to help of Micro Wind and DSCH to eliminate charge in the pull-down differential gate and remove the memory effect. |
Other Details |
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Paper ID: IJSRDV6I90390 Published in: Volume : 6, Issue : 9 Publication Date: 01/12/2018 Page(s): 489-493 |
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