A Systolic Hardware Architecture for Montgomery Modular Multiplication for Secure Data Communication

In modern communication systems, security is a main concern which is offered by cryptosystems Modular arithmetic is core operation in most of the cryptography systems. Most cryptosystems including RSA and DSA and ECC systems need modular multiplication for private key generation. That uses modular exponentiation function of large numbers to encrypt data, which is a slow process due to repeated modular multiplications. The efficiency of cryptography systems practically depends on how fast the multiplication is done. This is the base of computation. Most hardware and software designs for faster modular multiplication have been proposed, the Montgomery Multiplication Algorithm is recognized as the most efficient as others. This project that presents a 32 bit implementation of a Faster Montgomery algorithm for performing modular multiplication. The algorithm is based on the method proposed Montgomery for modular multiplication. The Simulation results shows that our design performs faster in terms of clock frequency while it requires lower Area and power.