A Review of High Performance Adder for Cryptography Algorithms

Arithmetic unit (AU) are the basic building blocks of microprocessors, microcontrollers and Digital Signal Processor. Adders are found to be the fundamental hardware unit for performing efficient arithmetic operations. A system that contains a pipeline architectures must have low power consumption, high speed and occupies medium area in implement which is the minimum requirement for today’s technology. In this paper different 16 bit adders are studied and design is implemented with and without pipeline. Various adders such as Ripple Carry Adder(RCA), Carry Increment Adder (CIA), Carry Look Ahead Adder (CLA), Carry Select Adder (CSeA) performance is analyzed in terms of area, power dissipation and critical path using cadence are simulated results and functionalities are also verified. Parameters like area and speed is compared with various implementations. Analysis concludes that pipelined carry save adder is the more efficient in speed and area consumption.