High speed Vedic multiplier using Urdhva Tiryagbhyam Sutra |
Author(s): |
| Shubham Kumar , Arya Institute of Engineering & Technology; Dhanesh Kumar, Arya Institute of Engineering & Technology; Bhawna Kalra, Rajasthan Technical University kota |
Keywords: |
| Vedic mathematics, Urdhva Tiryagbhyam, VHDL, Vedic multiplier |
Abstract |
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Vedic mathematics comes under the category of fast multipliers. In the field of communication different multipliers are used but they consume more power and they are less area efficient. Vedic multiplier gives high speed and its latency is also good. Proposed work presents a direct method of computing multiplication by using the Vedic mathematics sutra “Urdhva Tiryagbhyamâ€. The hardware implementation of proposed multiplier is done on FPGA. This can be used in many applications like FFT computation, Convolution, ALU, CPU, etc. The coding is done in VHDL. Simulation and synthesis are performed using the Xilinx ISE design suite 14.2 Simulated results for the proposed 2x2 bit Vedic multiplier circuit shows a reduction in delay as compare to previously made multipliers. |
Other Details |
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Paper ID: IJSRDV7I120398 Published in: Volume : 7, Issue : 12 Publication Date: 01/03/2020 Page(s): 543-546 |
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