Compare Efficiency of Different Multipliers using Verilog Simulation for DSP Application

The main objective of this project work is to design and simulate simple, appropriate and reliable multipliers for DSP processors. Multipliers are one amongst the foremost important arithmetic units in Microprocessors and DSPs and also a serious supply of power dissipation. Reducing the power dissipation of multipliers could be a key to satisfy the general power consumption of digital circuits and systems. During this paper a High speed and low space design for the Wallace tree using compressed multiplier is projected compared to area architecture. This design is employed in FIR Filter style. The simulation result for eight bit multipliers and 4 tap filters shows that the projected low area and delay architecture lowers the overall area and delay in comparison to array multiplier and Wallace tree using compressed multiplier design based filter. To develop the system blocks in Modelsim 6.4 c and Xilinx ISE13.2.To achieve simulation and synthesis of Spartan3E FPGA tools from Xilinx ISE is employed. Verilog HDL is employed for describing the hardware and system understanding language.