LBIST Design using Stumps Architecture |
Author(s): |
| Shubham Suke , Sinhgad College Of Engineering ; Pushpa M. Bangare, SCOE |
Keywords: |
| BIST, LBIST, LFSR, MISR, STUMPS |
Abstract |
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In modern era rapidly increasing complexity of IC designs makes testing of VLSI chips more difficult due to occurrence of faults in the VLSI chips. This lead to development of testing technology called Logic Built in Self-Test (L-BIST). Design of reconfigurable Linear Feedback Shift Register (LFSR) for VLSI IC testing is implemented in LBIST. Reconfigurable LFSR can be used in logic BIST for improvement in Fault coverage of IC testing. Self-Test Using MISR/Parallel SRSG (STUMPS) architecture is used in logic BIST. The main intention of this paper work is to understand the performance and design of LBIST using STUMPS for VLSI IC testing and analysing speed, fault coverage and power. |
Other Details |
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Paper ID: IJSRDV7I80221 Published in: Volume : 7, Issue : 8 Publication Date: 01/11/2019 Page(s): 455-458 |
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