Efficient Operand Divided Hybrid Adder for Error Tolerant Applications |
Author(s): |
| R. Ramya , SRI SHAKTHI INSTITUE OF ENGINEERING AND TECHNOLOGY; Dr. T. V. P. Sundararajan, SRI SHAKTHI INSTITUE OF ENGINEERING AND TECHNOLOGY; Ms. S. Savitha, SRI SHAKTHI INSTITUE OF ENGINEERING AND TECHNOLOGY; Ms. N. Janani, SRI SHAKTHI INSTITUE OF ENGINEERING AND TECHNOLOGY |
Keywords: |
| Adaptive Precision, Approximate Computing, Vitality Quality Scaling, Error Tolerant Frameworks, Low-Power Design, VLSI |
Abstract |
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Inexact expansion is a procedure to improve vitality utilization and yield quality in blunder tolerant applications. In earlier workmanship, bit truncation has been investigated as a switch to progressively ad lib vitality and quality. In this concise, an inventive piece truncation methodology is proposed to accomplish progressively smooth quality debasement contrasted with cutting edge truncation plans. The fundamental reason for existing is to maintain a strategic distance from the calculation in certain info cases and legitimately sidestep the yield sign utilizing the identification rationale. By this strategy, control utilization can be much progressively diminished in the VLSI structure frameworks. Notwithstanding that the proposed model likewise plans three distinct adders with the surmised processing done in the MSB part. |
Other Details |
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Paper ID: IJSRDV7I80446 Published in: Volume : 7, Issue : 8 Publication Date: 01/11/2019 Page(s): 507-510 |
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