64 X 64 Bit High Speed Floating Point Multiplier using Urdhva Triyagbhyam Algorithm

In VLSI systems like microprocessors and application specific DSP architectures, the arithmetic operation which is extensively used is “Multiplication�. This paper proposes an efficient method for IEEE 754 floating point multiplication which gives a better implementation in terms of delay and power. The overall performance of most of the systems is determined by the multipliers. The power efficient, faster and low area multiplier design decides the performance of the system. The speed of operation is increased compared with carry save Multiplier. Multiplication is the most time consuming operation. For this fast method of multiplication based on ancient Indian Vedic mathematics is used. Among various method of multiplication Urdhva Tiryagbhyam (Vedic mathematics) algorithm is used and multiplication is for 64 x 64 bits. It enables parallel generation of intermediate products, eliminates unwanted multiplication steps with zeros. This design using Urdhva Tiryagbhyam sutra exhibits less combinational delay, high speed and power utilization.