High-Speed Architectural Design of Hybrid ADC with Low Power Consumption

In the present digital world, where high-end technology ranging from radar, video recorder, sensors etc. are used to acquire the analog signal, which is converted to digital data, as the modern technology is based on digital data processing. The process of Analog to Digital data conversion is done using Analog to Digital Converters (ADC). The analog to digital converters are designed with very high precision and speed, this concept of precision and speed is be taken to the next level by introducing Hybrid Analog to Digital converter, which meets all the requirement of the future trends. Flash and Successive Approximation Register (SAR) Analog to Digital converters are the widely used because of its high speed and precision in the Very Large Scale Integration (VLSI) field. The Analog to Digital converter need to have high speed, low power consumption, with high accuracy with less area. In order to achieve these requirement for Hybrid Analog to Digital converter are required. This project work is based on Hybrid Flash-SAR Analog to Digital converter, which will meet the requirements of future technology by achieving high speed, accuracy and with low power consumption, which is implemented in the field of VLSI system design.